Technical Staff Engineer - Verification

This engineer will lead verification activities for next-generation FPGA subsystems and SoCs, combining constrained-random, formal, C-based, power-aware, and gate-level techniques. The position sits within the FPGA Business Unit and involves building scalable UVM environments, improving verification flows with AI/ML, and supporting silicon readiness. The engineer will work closely with design, architecture, emulation, hardware prototyping, and post-silicon teams to identify issues early and establish consistent validation practices. They will also mentor less-experienced engineers and contribute to methodology and tool automation. This opportunity suits an experienced SoC verification specialist with strong SystemVerilog and UVM expertise, broad subsystem knowledge, and excellent debugging and collaboration skills.