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Updated daily · Sep 26, 2026
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Advanced ASIC FPGA Design Engineer

General Dynamics Mission Systems (GDMS)Scottsdale, AZFull-time

This engineer will architect and implement FPGA designs using VHDL or Verilog for Xilinx and Microchip devices. Responsibilities include synthesis, place-and-route, timing optimization, simulation, automated testbench development, high-speed interface design, and hardware bring-up. The position works closely with systems, software, and verification engineers in an Agile environment and contributes to design reviews, technical documentation, and automated CI/CD development flows. Candidates should be experienced with FPGA timing analysis, high-speed digital design, on-chip bus protocols, and simulation tools such as QuestaSim or ModelSim. It suits an experienced hardware design professional interested in secure, mission-focused engineering work, with cryptography, serial communications, scripting, and embedded FPGA processor experience being advantageous.

Requirements

Bachelor’s degree plus 5 years of relevant experience, or master’s degree plus 3 yearsProficiency in VHDL and/or Verilog/SystemVerilog RTL designHands-on experience with Xilinx Vivado or Microchip LiberoExperience achieving timing closure at clock rates above 300 MHzKnowledge of FPGA simulation, self-checking testbenches, CDC, and high-speed digital designU.S. citizenship and ability to obtain or maintain a Secret clearance
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Listed September 17, 2026 · Verify details with the employer before applying.

About General Dynamics Mission Systems (GDMS)

Scottsdale campus develops advanced communications, cyber, and mission-critical electronics for defense and space programs.

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