Senior SoC Physical Layout & Full-Chip Integration Engineer

Intel · Phoenix, AZ · $122,440.00-$232,190.00 USD annually · Posted Sep 17, 2026

Intel is seeking a senior physical layout and integration engineer to lead custom layout methodology, full-chip implementation, verification closure, and tapeout for advanced-node silicon vehicles. The role connects physical design, process technology, PDK, EDA, and manufacturing teams to deliver scalable and manufacturable chip solutions.

Apply and full details on Arizona AI