Senior SoC Physical Layout & Full-Chip Integration Engineer

This engineer will own floorplanning, physical integration, database readiness, and tapeout execution for test chips and other silicon development platforms. The position sits within Intel Foundry’s Design Technology Platform organization and supports emerging process technologies, including FinFET and Gate-All-Around architectures. Key work includes resolving DRC, LVS, DFM, density, and antenna issues while improving layout flows through Tcl, Python, SKILL, or similar automation. The role also involves partnering with technology and PDK teams on design rules, physical verification, and design enablement. It suits an experienced custom or analog layout professional who can lead cross-functional projects, make decisions in ambiguous situations, and improve engineering quality and efficiency.