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Updated daily · Aug 27, 2026
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Principal Engineer - CAD (Physical Verification)

Microchip TechnologyChandler, AZ

This position sits within Microchip’s global CAD organization and focuses on physical verification for both digital and analog chip designs. The engineer will create regression tests, develop and enhance foundry rule decks, debug verification results, and support engineers using tools such as Calibre, Pegasus, and Hercules. The work includes advanced checks involving DRC, LVS, PERC, ERC, ESD, voltage-aware verification, and design-for-manufacturing methodologies across a broad range of process nodes and PDKs. The role also provides technical support to worldwide design sites and contributes to more reliable, efficient verification flows. It suits an experienced physical verification or CAD engineer with strong EDA scripting, semiconductor layout knowledge, and the ability to collaborate across engineering functions.

Requirements

Bachelor’s degree in Electrical Engineering or related field plus 10 years of physical verification experienceExpertise with Siemens Calibre and/or Cadence Pegasus physical verification toolsStrong knowledge of Calibre DesignRev, SVRF, and TVFProficiency with Tcl/Tk, Perl, Python, and EDA flow automationExperience debugging DRC/LVS/PERC issues and developing rule decksUnderstanding of layout rules, foundry requirements, DFM, quality, and yield
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Listed August 27, 2026 · Verify details with the employer before applying.

About Microchip Technology

Global microcontroller/analog semiconductor maker headquartered in Chandler since 1989.

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