Senior Engineer II - CAD (Physical Verification)

This position sits within Microchip’s global CAD organization and focuses on ensuring that chip layouts meet electrical, manufacturing, reliability, and foundry requirements. The engineer will create and improve DRC, LVS, PERC, ERC, and related verification flows, build regression coverage, validate foundry decks, and troubleshoot issues with design and layout teams. The work spans digital and analog designs, advanced process nodes, and tools such as Siemens Calibre, Cadence Pegasus, and Synopsys Hercules. Success requires strong scripting and software-development ability alongside practical knowledge of circuits, layout, device structures, and manufacturing rules. It is well suited to an experienced physical verification specialist who can collaborate across engineering groups and support teams located around the world.