Senior Static Timing Analysis (STA) Engineer

This engineer will own chip- and block-level static timing analysis, constraint development, timing rollups, PVT setup, and resolution of timing issues across complex SoC designs. The position works closely with architecture, logic, clocking, DFT, and physical design teams to guide clock-network development and achieve reliable timing convergence. It also contributes to scalable analysis flows, timing models, scripting, and physical design methodologies used across Intel programs. The role suits an experienced semiconductor professional who combines strong STA and clocking expertise with practical physical design knowledge, technical leadership, and effective cross-functional communication. Mentoring others and driving improvements through complex, fast-changing projects are also important aspects of the position.