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Principal Engineer - Standard Cell Design

IntelPhoenix, AZFull-time$220,920.00-$311,890.00 USD

As a Principal Engineer in Standard Cell Design at Intel, you will own the strategy and technical direction of standard cell library development, driving innovations in circuit design for high-performance and low-power applications. This role requires deep expertise in transistor-level physics, circuit design, and design-technology co-optimization, with responsibilities spanning from defining cell architecture and methodology to optimizing designs for Intel's most advanced process nodes. You'll work across multiple stakeholder groups including product design teams, foundry customers, EDA partners, and process technology teams to align on scalable solutions and drive technical convergence. The ideal candidate combines strong technical depth in analog and digital circuit design with proven leadership abilities, demonstrated through mentoring junior engineers, leading cross-functional working groups, and making high-impact decisions in complex, ambiguous environments. This position suits experienced engineers who are passionate about solving fundamental circuit challenges while building and developing technical talent within the organization.

Requirements

Ph.D. or Master's degree in electrical engineering or related field with 10+ years of industry experience in foundation IP design and advanced semiconductor technologyIn-depth understanding of MOSFET physics, transistor-level design of static circuits including latches and flip-flops, and standard cell characterization and Spice simulationExpertise in low-power and high-performance circuit design techniques, with strong knowledge of power-performance-area tradeoffs and variation impacts at advanced nodesProven ability to lead technical initiatives, mentor junior engineers, and drive cross-organizational alignment on complex technical challengesStrong analytical and communication skills with ability to identify trends in silicon data and translate complex challenges into practical, scalable solutionsPreferred: Technical leadership experience, exposure to layout effects, understanding of block-level design tools, and background in EDA tool interaction or compact modeling
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Listed July 14, 2026 · Verify details with the employer before applying.

About Intel

Four decades of chip manufacturing in Chandler, with the Ocotillo campus among Intel's largest fab sites and ongoing expansion.