This engineer will define library content and strategy, develop innovative sequential and clocking circuits, and optimize standard-cell solutions across Intel’s leading process nodes. The position works closely with foundry customers, process technology teams, product designers, DTCO groups, and EDA partners to close technology gaps and deliver scalable libraries. It also includes analyzing silicon and design data, improving characterization and validation methods, and resolving complex PPA and variability challenges. As a senior technical leader, the engineer will mentor designers, lead working groups, and help establish future circuit and library directions. The role suits an experienced semiconductor professional with deep transistor-level design expertise, strong communication skills, and a record of leading advanced foundation-IP or technology co-optimization work.

Key qualifications

Ph.D. or Master's degree in electrical engineering or related field with 10+ years of industry experience in foundation IP design and advanced semiconductor technology
In-depth understanding of MOSFET physics, transistor-level design of static circuits including latches and flip-flops, and standard cell characterization and Spice simulation
Expertise in low-power and high-performance circuit design techniques, with strong knowledge of power-performance-area tradeoffs and variation impacts at advanced nodes
Proven ability to lead technical initiatives, mentor junior engineers, and drive cross-organizational alignment on complex technical challenges
Strong analytical and communication skills with ability to identify trends in silicon data and translate complex challenges into practical, scalable solutions
Preferred: Technical leadership experience, exposure to layout effects, understanding of block-level design tools, and background in EDA tool interaction or compact modeling

Principal Engineer - Standard Cell Design