Senior Analog Mixed Signal Verification Engineer

This engineer will own verification planning and execution for complex PMIC blocks, subsystems, and SoCs, ensuring functional, performance, safety, reliability, and power requirements are thoroughly addressed. The position involves building reusable mixed-signal verification environments, behavioral models, assertions, checkers, and scoreboards with Verilog-AMS, SystemVerilog, UVM, and real-number modeling. The engineer will manage constrained-random testing, regressions, coverage analysis, requirements traceability, defect resolution, and signoff milestones while connecting analog and digital verification flows. Collaboration spans design, validation, architecture, applications, systems, product teams, and customers, with opportunities to improve methodologies and mentor less-experienced engineers. It suits a senior verification leader with deep AMS IC experience, strong PMIC knowledge, automation skills, and the ability to guide cross-functional development in a demanding product environment.