SoC Interconnect Technology Team Lead

This leader will guide the architecture, implementation, and delivery of interconnect fabrics supporting mobile, low-power, and high-performance computing platforms. The work includes defining topology and QoS strategies, evaluating latency, bandwidth, and power trade-offs, and coordinating integration with CPU, GPU, NPU, memory, and other system groups. The position also oversees performance modeling, RTL and verification direction, standards adoption, and resolution of complex system issues through tape-out and beyond. It is suited to an experienced SoC architect and people leader who has delivered large-scale chips and can shape roadmaps while mentoring engineers and influencing multiple subsystem teams.