Principal Engineer-Design (SoC Integration and RTL/IP)

This engineer will integrate processors, memories, peripherals, and custom IP into complete SoCs and subsystems using proprietary and AMBA bus protocols. They will create synthesizable SystemVerilog for reusable controllers, peripherals, wrappers, and power-management functions while addressing timing, lint, CDC, RDC, and synthesis issues. The position also includes FPGA implementation and validation, post-silicon debugging, ECO support, and maintenance of existing IP. As a senior technical contributor, the engineer will guide design reviews, mentor less-experienced engineers, and influence IP and product implementation decisions. It suits an experienced ASIC, SoC, RTL, and FPGA professional who can work independently and collaborate effectively across multidisciplinary hardware and software teams.