Open role
ADCE Packaging Design Architect
The engineer will own substrate design activities, including feasibility studies, routing, design-rule definition, design reviews, data analysis, and resolution of design-rule violations. This position works across silicon, hardware, and packaging teams to balance technical performance, manufacturability, and cost. It also requires maintaining design documentation and lifecycle records while supporting package verification and optimization. The role suits an experienced electrical, mechanical, chemical, or materials engineer with deep semiconductor packaging, PCB, or IC design expertise. Strong analytical judgment, independence, communication skills, and proficiency with industry design and simulation platforms are important for success.
Requirements
Listed September 11, 2026 · Verify details with the employer before applying.
About Intel
Four decades of chip manufacturing in Chandler, with the Ocotillo campus among Intel's largest fab sites and ongoing expansion.
More roles at Intel
- Senior Staff Process Integration Development EngineerPhoenix, AZ
- Substrate Quality and Reliability EngineerPhoenix, AZ
- AI Software Engineering PhD InternPhoenix, AZ
- Federal Program Associate - Intel Contract EmployeePhoenix, AZ
- Software Development EngineerPhoenix, AZ