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Updated daily · Sep 11, 2026
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ADCE Packaging Design Architect

IntelPhoenix, AZ$220,920.00-$311,890.00 USD annually

The engineer will own substrate design activities, including feasibility studies, routing, design-rule definition, design reviews, data analysis, and resolution of design-rule violations. This position works across silicon, hardware, and packaging teams to balance technical performance, manufacturability, and cost. It also requires maintaining design documentation and lifecycle records while supporting package verification and optimization. The role suits an experienced electrical, mechanical, chemical, or materials engineer with deep semiconductor packaging, PCB, or IC design expertise. Strong analytical judgment, independence, communication skills, and proficiency with industry design and simulation platforms are important for success.

Requirements

Advanced degree in electrical, chemical, mechanical engineering, or materials science10+ years of experience in package, PCB, or IC digital designStrong semiconductor fabrication and packaging knowledgeExperience with Cadence Allegro/APD or Mentor Xpedition toolsFamiliarity with SPICE, Ansys, Mentor, Cadence, or electromagnetic simulation toolsStrong problem-solving, organization, and communication skills
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Listed September 11, 2026 · Verify details with the employer before applying.

About Intel

Four decades of chip manufacturing in Chandler, with the Ocotillo campus among Intel's largest fab sites and ongoing expansion.

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