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Updated daily · Sep 13, 2026
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Senior Staff Collateral Design and DFM Engineer

IntelPhoenix, AZFull-time$161,550.00-317,600.00 USD

This engineer will help Intel Foundry move advanced logic technologies from development into stable high-volume manufacturing. The position leads cross-functional work on DFM rules, yield feedback, design flows, test-chip structures, scribe-line layouts, and design-rule governance. It also serves as a technical link between manufacturing organizations and foundry customers, translating silicon results into practical design and process improvements. The role is part of the Manufacturing Development Customer Engineering organization and supports customers with varied technical and market needs. It is well suited to an experienced semiconductor engineer with strong DTCO or DFM expertise, advanced-node layout and yield experience, and the communication skills to influence teams across the foundry ecosystem.

Requirements

Master's degree in Electrical Engineering, Physics, or related field6+ years of DTCO and/or DFM experience in semiconductor foundry or advanced technology developmentExpertise in DTCO methodologies including SRAM and Standard Cell designHands-on experience with advanced node test chip design and scribe line optimization at 3nm-16nm FinFET or sub-3nm GAA technologiesDemonstrated ability to lead cross-functional teams in defining design rules and device architecturesStrong communication skills with ability to manage multiple concurrent projects in fast-paced environment
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Listed June 30, 2026 · Verify details with the employer before applying.

About Intel

Four decades of chip manufacturing in Chandler, with the Ocotillo campus among Intel's largest fab sites and ongoing expansion.

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