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Updated daily · Sep 19, 2026
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Silicon Packaging Design Engineer

IntelPhoenix, AZ$105,650.00-$149,150.00 USD annually

This engineer will create and refine package substrate layouts while balancing silicon, package, board, manufacturing, performance, and cost requirements. Responsibilities include conducting fit and routing studies, defining design rules, resolving design-rule violations, and maintaining technical documentation throughout the product lifecycle. The position works closely with silicon, hardware, and other engineering teams to optimize pinouts and system-level interactions. It suits an early-career engineer with training in electrical, mechanical, or materials engineering and exposure to microelectronic packaging or PCB layout. Experience with package design tools, modeling software, or scripting would be advantageous, along with strong communication, organization, and problem-solving abilities.

Requirements

Bachelor’s degree plus 1+ year of experience, or a master’s degree with 6+ months of experience, in electrical, mechanical, or materials engineeringAt least 6 months of experience with microelectronic package or PCB layout and manufacturing processesFamiliarity with package design tools such as Siemens Xpedition, Cadence Allegro, AutoCAD, or SolidWorksUnderstanding of substrate layout, floor planning, custom layouts, or schematic-to-layout conversionStrong cross-functional communication, problem-solving, and project-management skillsPreferred: package substrate design, electrical modeling, automation tools, or Python/VB/C scripting experience
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Listed August 21, 2026 · Verify details with the employer before applying.

About Intel

Four decades of chip manufacturing in Chandler, with the Ocotillo campus among Intel's largest fab sites and ongoing expansion.

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