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Silicon Packaging Design Engineer
This engineer will create and refine package substrate layouts while balancing silicon, package, board, manufacturing, performance, and cost requirements. Responsibilities include conducting fit and routing studies, defining design rules, resolving design-rule violations, and maintaining technical documentation throughout the product lifecycle. The position works closely with silicon, hardware, and other engineering teams to optimize pinouts and system-level interactions. It suits an early-career engineer with training in electrical, mechanical, or materials engineering and exposure to microelectronic packaging or PCB layout. Experience with package design tools, modeling software, or scripting would be advantageous, along with strong communication, organization, and problem-solving abilities.
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Listed August 21, 2026 · Verify details with the employer before applying.
About Intel
Four decades of chip manufacturing in Chandler, with the Ocotillo campus among Intel's largest fab sites and ongoing expansion.
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