Principal SerDes Architect

This Principal Engineer position involves leading the architecture and development of high-speed IO PHYs with industry-leading performance, power, and area metrics. The role encompasses designing and optimizing analog circuits including transmitter and receiver blocks, creating detailed floorplans, simulating analog behavior, and developing comprehensive test plans. The successful candidate will serve as a recognized domain expert who influences technical direction both within Intel and across the industry while mentoring other technical leaders. This position suits experienced analog circuit designers with 12+ years of experience who have demonstrated technical leadership, expertise in SerDes and IO PHY design, and the ability to drive innovation in advanced process nodes.