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Updated daily · Sep 13, 2026
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Design Technology Tool Enablement Engineer

IntelPhoenix, AZFull-time$173,660.00-284,580.00 USD

This engineer will create, test, debug, and optimize EDA tools and design flows used by semiconductor development teams. The position sits within Intel’s Design Technology Platform organization and involves partnering with process engineers, design-rule owners, internal users, and external EDA suppliers. Responsibilities include automating workflows, defining tool requirements, developing rule decks, validating physical verification capabilities, and diagnosing performance issues. It suits an experienced semiconductor or EDA professional who combines programming ability with knowledge of process technology, design rules, and physical verification. Strong communication, independent problem solving, leadership, and cross-functional collaboration are important for success in this dynamic environment.

Requirements

Master's degree in Electrical/Computer Engineering or related STEM field with 8+ years experience, or Ph.D. with 5+ years3+ years scripting with Python, Tcl, or Perl for automation/testing on Unix/Linux platforms3+ years experience with EDA tools (Calibre, ICV, Pegasus) and rule deck development (SVRF/TVF, PXL, PVL)5+ years in semiconductor device physics, process technology, design rules, or translating design challenges into software solutionsStrong problem-solving, analytical, and communication skills with ability to work across teamsCreative, self-motivated engineer with attention to detail and leadership capability
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Listed July 8, 2026 · Verify details with the employer before applying.

About Intel

Four decades of chip manufacturing in Chandler, with the Ocotillo campus among Intel's largest fab sites and ongoing expansion.

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