SOC Physical Design Static Timing Analysis Engineer

This engineer will drive chip-level timing closure by evaluating constraints, violations, timing models, and PVT scenarios against product performance and power goals. The position contributes to clock network optimization, timing rollups, physical design execution, and integration flows for high-performance SoCs. It works closely with clocking, architecture, logic, DFT, and full-chip implementation teams to resolve tradeoffs involving timing, power delivery, partitioning, and functionality. The role also includes improving analysis tools, scripts, flows, and design methodologies. It suits an experienced digital implementation professional with strong STA and clocking expertise, practical physical design knowledge, and the ability to communicate and collaborate across technical organizations.