SOC Physical Design Static Timing Analysis Engineer

This position focuses on conducting comprehensive timing analysis at the system-on-chip level, identifying and resolving timing violations while optimizing clock networks for performance and power consumption. You will develop timing constraint methodologies, establish analysis conditions aligned with product requirements, and create efficient timing models that enable smooth physical design execution. Working alongside architecture, clocking, and design teams, you'll establish best practices and tools that improve the timing closure process across chip integration. The role suits experienced engineers who combine deep technical knowledge of timing analysis with strong cross-functional collaboration skills and a passion for solving complex performance challenges in leading-edge semiconductor design.