IP Design Verification Engineer

This engineer will own verification planning and execution for mixed-signal semiconductor IP, including testbench development, analog behavioral modeling, and validation of high-speed interfaces and low-power behavior. The work combines analog and digital debugging with SystemVerilog-based methodologies such as UVM and OVM, supported by commercial EDA tools. As part of Intel’s Central Engineering Group, the engineer will contribute to reusable IP, tools, and methodologies that support product and foundry programs. The position requires close collaboration across disciplines, technical documentation, reviews, and continuous improvement of verification infrastructure. It is well suited to an experienced electrical or computer engineer who can independently investigate complex issues and deliver reliable results under schedule pressure.