RTL Design Engineer

This role involves creating register transfer level designs and Verilog/SystemVerilog code for CPU cores and functional units that will be integrated into Intel's chip designs. The engineer works closely with architecture teams to translate microarchitecture specifications into synthesizable RTL, using optimization techniques to meet strict power, performance, area, and timing requirements. The position requires reviewing verification plans, debugging failed simulations, and documenting design specifications to support both internal teams and external SoC customers. This role suits engineers with a strong foundation in digital design and computer architecture who are comfortable working with EDA tools and scripting languages in a collaborative, fast-paced environment.