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Silicon Packaging Design Engineer
This engineer will own key aspects of interposer and bridge layout development, including routing, substrate fit analysis, and package-to-board integration studies. They will work with silicon, hardware, and technology teams to refine pinouts, packaging rules, and design solutions throughout the product lifecycle. The position involves using leading EDA tools, reviewing design data, resolving DRC issues, and documenting specifications for traceability. It sits within Intel Foundry’s advanced packaging organization, supporting semiconductor products for modern computing and connectivity applications. The role suits an experienced electrical, computer, or related STEM engineer who is comfortable with silicon physical design and cross-functional technical problem-solving.
Requirements
Listed June 30, 2026 · Verify details with the employer before applying.
About Intel
Four decades of chip manufacturing in Chandler, with the Ocotillo campus among Intel's largest fab sites and ongoing expansion.