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Silicon Packaging Design Engineer

IntelFull-time$105,650.00-$200,340.00 USD

This position focuses on the physical design and layout of advanced silicon packaging components, particularly interposers and bridges that integrate silicon with broader system architectures. The engineer will use specialized design tools to create optimized routing and layouts while performing tradeoff analysis between performance, cost, and manufacturing feasibility. The role requires close collaboration with silicon designers, technology teams, and hardware engineers to ensure seamless integration across the silicon-package-board interface. This position suits engineers with strong EDA tool expertise and experience in physical design who are passionate about solving complex packaging challenges in a fast-paced semiconductor environment. The work contributes directly to Intel's foundry operations, which manufactures advanced compute devices for global markets.

Requirements

Bachelor's degree with 3+ years OR Master's degree with 2+ years in Electrical Engineering, Computer Engineering, or STEM fieldProficiency in EDA tools: Virtuoso, Innovus, FusionCompiler, ICvalidator, and/or CalibreExperience with silicon physical layout design, routing interconnects, and review tools1+ year experience in one of: Analog/Mixed Signal fundamentals, Power Distribution/integrity, or interconnect reliabilityStrong collaboration and technical communication skills across multi-disciplinary teamsAbility to conduct design tradeoff studies and optimize for performance, cost, and manufacturability
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Listed June 30, 2026 · Verify details with the employer before applying.

About Intel

Four decades of chip manufacturing in Chandler, with the Ocotillo campus among Intel's largest fab sites and ongoing expansion.