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Updated daily · Sep 13, 2026
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Silicon Packaging Design Engineer

IntelPhoenix, AZFull-time$105,650.00-$200,340.00 USD

This engineer will own key aspects of interposer and bridge layout development, including routing, substrate fit analysis, and package-to-board integration studies. They will work with silicon, hardware, and technology teams to refine pinouts, packaging rules, and design solutions throughout the product lifecycle. The position involves using leading EDA tools, reviewing design data, resolving DRC issues, and documenting specifications for traceability. It sits within Intel Foundry’s advanced packaging organization, supporting semiconductor products for modern computing and connectivity applications. The role suits an experienced electrical, computer, or related STEM engineer who is comfortable with silicon physical design and cross-functional technical problem-solving.

Requirements

Bachelor's degree with 3+ years OR Master's degree with 2+ years in Electrical Engineering, Computer Engineering, or STEM fieldProficiency in EDA tools: Virtuoso, Innovus, FusionCompiler, ICvalidator, and/or CalibreExperience with silicon physical layout design, routing interconnects, and review tools1+ year experience in one of: Analog/Mixed Signal fundamentals, Power Distribution/integrity, or interconnect reliabilityStrong collaboration and technical communication skills across multi-disciplinary teamsAbility to conduct design tradeoff studies and optimize for performance, cost, and manufacturability
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Listed June 30, 2026 · Verify details with the employer before applying.

About Intel

Four decades of chip manufacturing in Chandler, with the Ocotillo campus among Intel's largest fab sites and ongoing expansion.

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