CPU RTL Design Engineer

This engineer will create and refine RTL for CPU components and IP blocks that are integrated into complete chip designs. The work includes shaping architectural features, documenting microarchitecture, supporting verification, debugging failing tests, and ensuring designs are ready for physical implementation. The position sits within Intel’s Silicon and Platform Engineering organization and involves collaboration with SoC customers and other engineering teams. It is well suited to a senior hardware designer with substantial Verilog or SystemVerilog experience and a strong background in low-power, high-frequency CPU logic. Experience with x86 architecture, power management, timing analysis, scripting, and clock-domain or power-aware design would be especially valuable.