DFT Application Engineer

This engineer will support foundry customers with PDKs, DFT/DFM insertion, ATPG, timing signoff, and related design flows at both block and SoC levels. The position sits within Intel’s Central Engineering and Foundry Enablement organization, requiring close collaboration with customer design teams, IP suppliers, EDA vendors, and internal engineering groups. Responsibilities include improving DFT methodologies, developing flows for advanced and multi-die technologies, resolving implementation issues, and producing training and best-practice materials. The role is well suited to an experienced ASIC or semiconductor design engineer who enjoys customer-facing technical problem solving and cross-functional collaboration. Because the work supports aerospace, defense, and government programs, US citizenship and eligibility for a government security clearance are required.