Senior CPU RTL Design Engineer

This engineer will create and refine SystemVerilog RTL and simulation models for CPU functional units, IP blocks, and related logic. Responsibilities include shaping microarchitectural specifications, debugging failed tests, reviewing verification coverage, and supporting physical implementation through timing- and power-aware design methods. The position is part of Intel’s CPU Design organization and involves collaboration with architects, verification engineers, integration teams, and SoC customers. It suits an experienced CPU designer who is comfortable owning complex deliverables and solving problems analytically across the processor development lifecycle. Knowledge of x86 architecture, power management, clock-domain crossings, timing analysis, and scripting would be valuable for success.