Senior CPU RTL Design Engineer – Power Management

This senior engineering role involves designing and implementing CPU microarchitecture with a strong emphasis on power management and energy efficiency. You'll develop RTL code for CPU IP blocks, optimize power/performance/area trade-offs, and lead multi-clock domain design and power state management features like DVFS and thermal control. The role suits experienced engineers who can operate independently, debug complex systems, and drive architectural decisions across cross-functional teams without requiring extensive ramp-up time. You'll partner with architecture, verification, and physical design teams to deliver cutting-edge silicon while contributing to design methodology improvements. This position is ideal for engineers with deep low-power CPU/SoC expertise who thrive in fast-paced environments and take ownership of technical problems.