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Analog Engineer
This engineer will design and optimize circuits such as data converters, voltage regulators, and high-speed I/O interfaces within Intel’s Advanced Design Foundational IP organization. The work spans simulation, floorplanning, modeling, verification planning, layout collaboration, silicon implementation, and debugging after fabrication. The engineer will partner with architecture, layout, process technology, IP, and product teams to balance power, performance, area, timing, robustness, and yield. The position suits a senior analog or mixed-signal designer with substantial CMOS experience and a record of delivering circuits through tape-out. Experience with links, clocking, PLLs, power delivery, RF, or integrated regulators would be especially valuable.
Requirements
Listed July 7, 2026 · Verify details with the employer before applying.
About Intel
Four decades of chip manufacturing in Chandler, with the Ocotillo campus among Intel's largest fab sites and ongoing expansion.