EDA Tools SW Engineer

This position sits within Intel Foundry’s Design Enablement organization and leads a team supporting customer ASIC design flows, EDA tools, physical verification runsets, and test-chip signoff activities. The successful candidate will coordinate with technology development groups, EDA vendors, Intel design teams, and external customers to solve complex design and process challenges. Responsibilities include setting priorities, allocating resources, mentoring engineers, driving execution, and maintaining delivery against quality, cost, and schedule goals. The role suits an experienced semiconductor engineering leader with strong knowledge of advanced-node physical design or verification and a record of influencing cross-functional teams. It is based in the United States with a hybrid work model and may be located in Oregon, Arizona, California, or Texas.