Senior Manager- SOC Verification

This leader will guide a team of more than 20 verification engineers responsible for validating MCU-based SoCs from planning through tape-out. The position oversees UVM and formal verification architectures, coverage and regression infrastructure, power-aware analysis, and hardware-software co-verification. It involves close cooperation with architecture, RTL, DSP, and physical design groups to address integration risks and improve first-pass silicon results. The role is suited to an experienced semiconductor verification manager with substantial MCU tape-out experience, strong technical depth, and a record of developing engineering talent. Candidates should be comfortable balancing strategic planning, hands-on technical direction, resource management, and methodology improvement.