Sr. Logic Design Engineer

This position is part of Intel's Hardware IP Design team, focused on creating and refining logic designs for high-speed interface IP blocks that power Intel's datacenter infrastructure. The engineer will be responsible for RTL coding in SystemVerilog, architecting digital circuits, performing timing and power analysis, and working closely with verification teams to ensure designs meet performance and reliability requirements. The role requires someone who can quickly master complex IP specifications, work effectively across geographies and organizational boundaries, and balance multiple design priorities in a fast-paced environment. It's ideal for senior engineers with strong SystemVerilog skills, experience in data path and clock domain crossing design, and a track record of delivering high-quality RTL that meets stringent power and timing targets.