Sr. Logic Design Engineer

This engineer will join Intel’s HIPD organization and contribute to the logic design of UCIE PHY intellectual property used in flagship server platforms. Responsibilities span block architecture and microarchitecture, SystemVerilog RTL development, simulation, synthesis readiness, and design optimization. The role also involves reviewing verification coverage, diagnosing failed tests, and coordinating fixes across engineering teams and locations. Success requires strong analytical abilities, communication skills, adaptability, and the capacity to manage several priorities in a fast-moving environment. It is well suited to an experienced hardware designer with a background in front-end IP development, power and clock-domain considerations, and industry-standard design and simulation tools.