Senior SoC Compute/Memory Subsystem Architect

The Senior SoC Compute/Memory Subsystem Architect leads end-to-end design of compute complexes and high-performance memory subsystems for Intel's advanced IPU/DPU platforms serving hyperscale data centers and AI workloads. This position encompasses defining CPU cluster architectures, multi-level cache hierarchies, coherency models, memory controllers, IO virtualization (SMMU/IOMMU), and system-level integration across compute, networking, storage, and accelerator subsystems. The role requires balancing complex tradeoffs in performance, power efficiency, area, and scalability while driving multi-generation product roadmaps and collaborating across cross-functional teams including networking, firmware, and validation. The ideal candidate is a strategic technical leader with deep SoC architecture experience who can translate real-world hyperscale workload requirements into innovative silicon solutions and mentor other architects across the organization.