Principal Collateral Device Engineer

This engineer will guide the creation and optimization of device architectures, interconnect structures, scribe-line layouts, monitoring patterns, and related design rules for leading-edge process nodes. The position sits within Intel Foundry’s Manufacturing Development and Customer Engineering organization and connects process integration, yield, device engineering, and design teams. Responsibilities include interpreting test-chip results, applying statistical analysis and DOE methods, managing rule validation and waivers, and balancing manufacturing requirements with customer design flexibility. The successful candidate will be an influential technical leader who can operate across global, multidisciplinary teams in a high-volume manufacturing setting. It is well suited to an experienced CMOS engineer with deep expertise in advanced-node test chips, device collateral, design-rule flows, and process optimization.