Senior DfT Engineer

This engineer will define chip testability requirements with design, product, validation, quality, and test stakeholders, then create DfT architectures and RTL using Verilog and SystemVerilog. Responsibilities include verification planning, chip-level test development, scan-chain implementation and optimization, test-point insertion, ATPG generation, and debug of test patterns. The engineer will also assist with silicon bring-up and customer-return investigations while maintaining detailed architecture and design documentation. The position sits within an experienced DfT-focused engineering team and suits someone who combines strong digital design fundamentals with practical test methodology expertise. Candidates should be comfortable solving complex problems collaboratively and working regularly from NXP's Chandler, Arizona office.