Senior Principal Mixed Signal Design Engineer (Hybrid)

This engineer will guide ROIC and mixed-signal ASIC development from architecture and circuit design through verification, fabrication, testing, debugging, and documentation. The work includes analog signal chains, digital timing and processing, low-power 12–14 bit ADCs, system simulation, physical implementation, and power and timing evaluation. The role coordinates experienced engineers and communicates technical progress to senior customers and government stakeholders. It is well suited to an accomplished semiconductor or mixed-signal leader with extensive CMOS design experience, strong modeling and verification skills, and a background delivering complex programs in aerospace, defense, space, or commercial settings. U.S. citizenship is required, and the position supports hybrid work in Goleta or Phoenix.