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Packaging Research and Development Engineer
This engineer will establish equipment setups, process specifications, and integrated manufacturing flows for emerging substrate packaging technologies. The work includes designing experiments, defining process windows, analyzing interactions among tools and materials, and improving capability, yield, reliability, cost, automation, and productivity. The position sits within Intel’s backend module engineering and substrate packaging technology development organization, supporting cross-functional teams and external suppliers. It is suited to an experienced engineer with a background in semiconductor manufacturing, process or materials development, and strong troubleshooting and communication abilities. The role is based on-site in Phoenix, Arizona, with limited travel and flexibility needed for evolving responsibilities and work schedules.
Requirements
Listed August 11, 2026 · Verify details with the employer before applying.
About Intel
Four decades of chip manufacturing in Chandler, with the Ocotillo campus among Intel's largest fab sites and ongoing expansion.