Skip to main content
An independent guide to Arizona’s AI economyData refreshed daily · Aug 18, 2026
All open roles

Open role

Senior Density Fill Development Engineer

IntelPhoenix, AZ$128,880.00-$245,160.00 USD annually

This engineer will build, debug, validate, and deploy fill components for PDKs using industry-standard physical verification platforms such as Calibre, ICV, and Pegasus. The position partners with process technology teams, design-rule owners, end users, and EDA vendors to solve density and manufacturability challenges in advanced technology nodes. Responsibilities also include rule-deck development, test infrastructure, workflow automation, tool integration, documentation, and customer support. The role is suited to an experienced physical verification or semiconductor process-design professional with strong Unix/Linux, design-rule, and algorithm-development skills. Candidates with foundry, IDM, advanced packaging, or EDA vendor experience and a history of leading cross-functional improvements would be especially well matched.

Requirements

Bachelor’s degree with 8+ years, master’s with 5+ years, or PhD with 2+ years of relevant experience5+ years using Calibre, ICV, Pegasus, or another physical verification platform3+ years developing or debugging SVRF, TVF, PXL, PVL, or PVTCL rule decksKnowledge of semiconductor process technology, device physics, and design rulesExperience creating density-fill methodologies for 16nm-and-below technologiesStrong Unix/Linux, analytical, communication, and cross-functional collaboration skills
Apply for this role

Listed August 18, 2026 · Verify details with the employer before applying.

About Intel

Four decades of chip manufacturing in Chandler, with the Ocotillo campus among Intel's largest fab sites and ongoing expansion.