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Senior Density Fill Development Engineer
This engineer will build, debug, validate, and deploy fill components for PDKs using industry-standard physical verification platforms such as Calibre, ICV, and Pegasus. The position partners with process technology teams, design-rule owners, end users, and EDA vendors to solve density and manufacturability challenges in advanced technology nodes. Responsibilities also include rule-deck development, test infrastructure, workflow automation, tool integration, documentation, and customer support. The role is suited to an experienced physical verification or semiconductor process-design professional with strong Unix/Linux, design-rule, and algorithm-development skills. Candidates with foundry, IDM, advanced packaging, or EDA vendor experience and a history of leading cross-functional improvements would be especially well matched.
Requirements
Listed August 18, 2026 · Verify details with the employer before applying.
About Intel
Four decades of chip manufacturing in Chandler, with the Ocotillo campus among Intel's largest fab sites and ongoing expansion.