Senior Technical Staff Engineer - Verification

This engineer will design and maintain UVM and formal verification environments, create verification strategies, and use SystemVerilog assertions and coverage analysis to achieve closure. The position supports both IP and SoC verification, requiring close coordination with architects, RTL designers, applications groups, and geographically distributed teams. Responsibilities also include debugging, root-cause investigation, mentoring verification engineers, and improving processes through automation and AI/ML techniques. It is well suited to an experienced verification specialist who can lead complex projects, communicate effectively across organizations, and uphold high quality standards. The position is based in Chandler, Arizona, with expected travel of 0% to 25%.