Analog Design Engineer

This engineer will join Intel’s Central Engineering Hard IP and Test Chip Development organization, supporting analog and mixed-signal interfaces used by client, datacenter, AI, and foundry products. Responsibilities include designing analog blocks, running SPICE and Cadence simulations, creating validation plans, debugging circuit behavior, and partnering with layout engineers on implementation. The position also contributes to design reviews, technical documentation, reporting, and coordination with architecture, logic, validation, and SoC teams. It suits an electrical or computer engineer with practical analog IC experience, strong analytical skills, and familiarity with I/O, TX/RX, signal integrity, power integrity, and layout considerations. The role is based on-site in Phoenix, Arizona, or Hillsboro, Oregon, with an expectation of working in the office at least four days per week.