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An independent guide to Arizona’s AI economyData refreshed daily · Aug 14, 2026
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Senior Manager, Analog & Mixed-Signal Design Engineering

IntelPhoenix, AZ$164,470.00-$269,100.00 USD annually

This position leads an analog and mixed-signal engineering team within Intel’s Central Engineering Group, supporting IP used across client, data center, AI, and foundry platforms. The leader oversees work spanning architecture, circuit design, verification, silicon bring-up, validation, and production readiness for technologies such as clocking, converters, voltage regulation, and high-speed serial interfaces. Responsibilities include setting technical strategy, managing schedules and risks, coordinating distributed teams, and improving engineering processes through automation and data-informed execution. The role also emphasizes recruiting, mentoring, and building a strong organization while partnering with architecture, layout, validation, manufacturing, and product teams. It suits an experienced analog or mixed-signal engineering manager who combines deep silicon expertise with strategic leadership, communication, and organizational development skills.

Requirements

Bachelor’s degree in electrical, electronics, or related engineering field with 9+ years of experience6+ years in people, technical, project, or engineering management leadership8+ years delivering analog or mixed-signal IP through silicon validation and deployment7+ years of analog design experience involving areas such as noise, jitter, stability, matching, or linearity7+ years of silicon bring-up, post-silicon validation, and laboratory debugExperience with high-speed I/O or analog technologies such as PLL, CDR, ADC, TX/RX, PCIe, CXL, USB Type-C, or UCIe
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Listed August 14, 2026 · Verify details with the employer before applying.

About Intel

Four decades of chip manufacturing in Chandler, with the Ocotillo campus among Intel's largest fab sites and ongoing expansion.