Principal Engineer-Design

This engineer will guide digital blocks and subsystems from architectural definition through tape-out, creating reusable Verilog/SystemVerilog RTL for microcontroller peripherals and related IP. Responsibilities include leading simulation and coverage activities, low-power and mixed-signal verification, timing and power closure, and collaboration with physical design teams on implementation and signoff. The position works closely with architecture, analog, validation, test, product, applications, and marketing groups to ensure successful silicon development. It also involves design reviews, documentation, debugging, planning, and cross-team technical coordination. The role suits an experienced ASIC/SoC designer who combines strong digital fundamentals with practical integration knowledge, scripting ability, and an ownership-oriented leadership style.