Substrate Packaging Defect Metro Tool Owner

This engineer will support Intel’s SPTD Yield organization by developing and managing defect metrology capabilities for technologies such as glass core, EMIB-T, and panel-level packaging. The work includes analyzing inspection data, identifying process problems, coordinating corrective actions, and helping factory teams meet yield and production targets. The engineer will also lead the lifecycle of new metrology equipment, from specification and supplier engagement through qualification, installation, automation connectivity, and roadmap planning. Success requires close collaboration with process, module, manufacturing, supply chain, and equipment partners, along with the ability to communicate technical findings to leadership. The position suits an experienced semiconductor professional with strengths in yield engineering, contamination control, statistical analysis, Python, and independent project ownership.