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An independent guide to Arizona’s AI economyData refreshed daily · Aug 21, 2026
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Senior CPU RTL Design Engineer

IntelPhoenix, AZ$141,910.00-$269,100.00 USD

This engineer will help shape CPU architecture and microarchitecture while implementing, simulating, and debugging SystemVerilog RTL. The work focuses on meeting power, performance, area, timing, and physical implementation objectives for next-generation processors. The position operates within Intel’s CPU design organization and requires close partnership with architecture, verification, physical design, SoC integration, and validation teams. Responsibilities also include documenting design specifications, reviewing verification coverage, resolving test failures, and supporting integration with SoC customers. It suits an experienced hardware designer who can lead complex deliverables, communicate technical tradeoffs clearly, and influence decisions across engineering teams.

Requirements

Bachelor’s or master’s degree in electrical/computer engineering, computer science, or a related STEM field, with 7+ or 5+ years of relevant experience7+ years of SystemVerilog RTL design and hardware debugging experience5+ years working with low-power design and high-frequency optimization techniques5+ years of clock-domain crossing and power-aware design experience3+ years using TCL, Perl, Python, or similar scripting languagesKnowledge of CPU architecture, power management, timing analysis, UPF, and linting is preferred
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Listed August 21, 2026 · Verify details with the employer before applying.

About Intel

Four decades of chip manufacturing in Chandler, with the Ocotillo campus among Intel's largest fab sites and ongoing expansion.