Semiconductor Packaging Research Engineer

This engineer will explore technologies such as chiplets, 2.5D/3D integration, hybrid bonding, interposers, and die-to-die connections. Depending on their background, they may lead experimental integration work involving research vehicles, design of experiments, defect learning, and qualification, or develop and validate thermal, mechanical, electrical, and reliability models. The position translates product challenges into research plans and communicates findings through technical reports, design guidance, intellectual property, publications, and development handoffs. It operates within a broad Intel ecosystem involving research, design, materials, manufacturing, reliability, suppliers, universities, and industry partners. The role suits engineers with graduate training and practical experience in semiconductor packaging, advanced integration, simulation, reliability, materials, or related fields who can turn uncertain technical questions into actionable recommendations.